What are the ‘Heat Sink’ capabilities of the BB-400?

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Compute Module CM3+ Thermal Improvement

The BB-400 uses the latest Raspberry Pi Compute Module CM3+ with 32GB of on-board non-volatile storage. This version of the Compute Module features a small metal heat sink cover that sits atop the Broadcom SoC. Previous versions have not had this metal heat sink and have operated at higher processor temperatures as a result. Brainboxes have extended this heat sinking capability even further by adding a larger heat sink which is in direct thermal contact with the CM3+ metal cover.

Brainboxes Heat Sink Tests

The picture below shows the Brainboxes Heat Sink that will be included with the product as standard. The Heat Sink is composed of lightweight Aluminium and exhibits a finned construction so as to maximise the surface area. When installed in the BB-400 as shown below, the fins are oriented along the length of the compute module PCB so as to align with the vent openings in the BB-400’s cover. If the BB-400 is DIN rail mounted inside a cabinet for example, this cooling capability can be taken full advantage of if the unit is mounted in a vertical orientation so as to allow heat convection.

Temperature testing has been carried out using the Brainboxes Heat Sink along with a CM3+ at room temperature. The compute module was loaded with varying percentages of CPU usage from <1% all the way up to 100% on all four ARM cores and the temperature increase of the Broadcom SoC was recorded. This test was repeated with the CM3+ on its own (without the Brainboxes Heat Sink attached) and with the CM3 on its own (no metal cover) and the results compared. All tests were done with the default Frequency Scaling Governor setting in the Raspberry Pi, which is set to the ondemand policy.

The Frequency Scaling Governor ondemand policy is a standard feature of the Raspberry Pis which controls the processor core clock speed according to the CPU Usage load level and the internal temperature of the SoC. Typically, for average loads that are less than a default threshold of 50%, the processor runs all four ARM cores at a minimum clock speed of 600MHz. As the load level rises above 50% the SoC switches the core clock frequency to the maximum value of 1200MHz in order to obtain maximum performance. This clock frequency setting remains until either the load level drops back below 50% or the internal temperature of the processor exceeds 80 degrees C. In the case where the temperature rises above 80 degrees C, the clock frequency is throttled back to a value between 1200MHz and 600MHz in a continuous scale so as to limit the temperature to no more than 80 degrees C.

The graph below shows the results of the temperature testing for three cases, the CM3 on its own, the CM3+ on its own and the CM3+ with the Brainboxes Heat Sink attached. In all tests, the BB-400 was fully cased and mounted in a vertical orientation so as to represent a typical use scenario. All four operating regions corresponding to the Frequency Scaling Governor ondemand policy are illustrated on the graph and overlaid on the results for the three temperature profiles:

For each measurement case, it can be seen that at low CPU Usage loads the core clock frequency stays constant at the lowest value of 600MHz. As load increases the temperature of the SoC above ambient also increases until periodic fluctuations of core load above 50% cause the core clock frequency to randomly change between the two discrete values of 600MHz and 1200MHz. In this region the rate of temperature rise increases with further increases in CPU Usage load until eventually the overall average load exceeds the governor threshold of 50%. This marks the transition to the third operating region in which the core clock frequency remains fixed at 1200MHz. The temperature rise at this point is seen to jump considerably to higher values which is consistent with the sudden change of core clock frequency to maximum and thus a corresponding increase in power consumption. Further increases in CPU Usage load then cause the temperature rise to continue until eventually the rise exceeds 57 degrees C above ambient, which relates to an internal SoC temperature of 57+23=80 degrees C.

For the CM3 on its own, the load at which the SoC temperature exceeds 80 degrees C is ~40%. Above this value the temperature rise begins to flatten as the Frequency Scaling Governor throttles the core clock frequency to values <1200MHz in order to limit any further temperature rise. For the CM3+ on its own, the value of load at which the throttling occurs is increased to ~68% and with the Brainboxes Heat Sink attached, this load value is further improved to nearly 100% at 23 degrees C ambient temperature. The throttled values of core clock frequency at 100% load are displayed for each measurement case. It can be seen that for the CM3 on its own the frequency is throttled all the way down to the minimum ~600MHz whereas for the CM3+ the reduction only reaches ~800MHz. For the CM3+ with Brainboxes Heat Sink, the throttled core clock frequency is only very slightly reduced from 1200MHz to ~1190MHz.

NOTE: These results were obtained at an ambient temperature of 23°C. As ambient temperature increases, the SoC temperature will also increase for fixed CPU Usage load conditions, regardless of heat sinking configuration. Therefore, the CPU Usage load threshold for throttled clock frequency will move to lower values (<100%) as ambient temperature rises. This effect is not related to the operating temperature range of the BB-400, which is purely a hardware specific parameter.

Conclusion

It has been shown that the addition of the Brainboxes Heat Sink to the Raspberry Pi CM3+ dramatically improves performance compared to either the CM3 or the CM3+ on its own. In each case the thermal improvements show an overall reduction in the amount of SoC temperature rise across the entire CPU Usage range. The BB-400 with Brainboxes Heat Sink is the only case which shows practically no core speed performance degradation and thus maintains maximum performance throughout the CPU Usage range.

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